The present invention relates to a semiconductor memory device, and more particularly, to a data output control circuit that can control the timing of data output so that data corresponding to an external command can be outputted in synchronism with a system clock.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor in unit cells selected according to addresses inputted together with the data.
As the operating speed of the system is increasing, the data processor requires the semiconductor memory device to output and store data at higher speed. For the purpose of high-speed data input and output, a synchronous memory device was developed. The synchronous memory device inputs and outputs data in synchronism with a system clock. However, because even a synchronous memory device could not meet the required data input/output speed, a double data rate (DDR) memory device was developed. The DDR memory device outputs or inputs data at falling edges and rising edges of the system clock.
The DDR memory device must process two data elements during one cycle of the system clock so as to input and output data at a falling edge and a rising edge of the system clock. Specifically, the DDR memory device must output data exactly in synchronism with the rising edge and the falling edge of the system clock. To this end, a data output circuit of the DDR memory device outputs data in synchronism with rising and falling edges of the system clock.
The semiconductor memory device must output data corresponding to an external read command several periods of the system clock after the input of the external command. A column address strobe (CAS) latency (CL) represents the timing of the start of the data output. Generally, the semiconductor memory device supports multiple CLs and can adjust them according to operation environment. The CL is set in a mode register set (MRS). When the external read command is inputted, the semiconductor memory device determines the timing of data output according to the CL set in the MRS.
However, the system clock inevitably is delayed until it arrives at a data output circuit because it passes through a clock input buffer, a clock transmission line, etc. Thus, if the data output circuit outputs data in synchronism with the delayed system clock, an external device will receive data that are not synchronized with rising edges and falling edges of the system clock. To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) circuit to lock a delay of a clock signal. The DLL circuit 450 compensates the delay caused by internal circuits of the semiconductor memory device until the system clock inputted to the semiconductor memory device is transferred to the data output circuit.
In order to output the data in exact correspondence to the external command after the CL, the semiconductor memory device uses a data output control circuit that determines the timing if data output by using a DLL clock outputted from a DLL circuit 450 and a CL set in an MRS. After outputting the DLL clock, the DLL circuit 450 stops the delay locking operation so as to reduce the power consumption when the clock phase is not changed by the change of operation mode or environment of the semiconductor memory device. However, the data output control circuit can continuously output data by using the DLL clock whose phase already has been locked.
FIG. 1 is a block diagram of a data output control circuit in a conventional semiconductor memory device. The data output control circuit outputs data in synchronism with a (DLL) clock outputted from a DLL circuit 450, or outputs data in synchronism with an external system clock when the DLL circuit 450 does not perform the delay locking operation.
Referring to FIG. 1, the data output control circuit includes a first timing computation unit 120, a second timing computation unit 140, and a data output timing computation unit 160. The first timing computation unit 120 counts a DLL clock outputted from a DLL circuit 450, and the second timing computation unit 140 counts an external system clock. The data output timing computation unit 160 determines data output timing by detecting a timing at which an output of the first timing computation unit 120 is equal to an output of the second timing computation unit 140 when an external command is inputted.
Specifically, the first timing computation unit 120 includes a DLL reset synchronizer 122, an initial value determining unit 126, and a first clock counter 124. The second timing computation unit 140 includes an external clock synchronizer 142, a latch 144, a multiplexer 146, and a second clock counter 148. The data output timing computation unit 160 receiving the output of the first timing computation unit 120 and the output of the second timing computation unit 140 includes a comparator 162, a signal generator 164, and an output enable signal output buffer 166.
The DLL reset synchronizer 122 of the first timing computation unit 120 outputs a DLL reset signal DLLRST indicating a timing at which an output reset signal OERST is deactivated to a logic low level in synchronism with a DLL clock RCLKDLL outputted from a DLL circuit 450, that is, a timing at which the semiconductor memory device exits a reset state. The output reset signal OERST is activated according to an operation mode of the semiconductor memory device. When the semiconductor memory device enters a power-down mode, the output reset signal OERST is activated to a logic high level to reset an output enable signal OE. When the output reset signal OERST is deactivated to a logic low level in response to an external active signal, the semiconductor memory device exits the reset state. The DLL reset signal DLLRST is inputted to the first clock counter 124 to count the DLL clock outputted from the DLL circuit 450. An initial value of the first clock counter 124 is determined by the initial value determining unit 126. The determined initial value can be changed according to designs, but is dependent on a column address strobe (CAS) latency (CL).
The DLL reset signal DLLRST outputted from the DLL reset synchronizer 122 is inputted to the second timing computation unit 140 through a replica delay line 130. The replica delay line 130 compensates a phase difference between the external system clock and the DLL clock. Generally, the replica delay line 130 is similar to a replica delay circuit of the DLL circuit 450 and models a delay value that the system clock experiences within the semiconductor memory device.
The second timing computation unit 140 receives a delayed DLL reset signal DLLRST_REP from the replica delay line 130 and outputs a counting result of a rising edge of the system clock. The external clock synchronizer 142 receives the delayed DLL reset signal DLLRST_REP and an external clock bar signal EXTCLKB. The external clock synchronizer 142 transfers the delayed DLL reset signal DLLRST_REP in synchronism with the falling edge of the system clock, and the latch 144 latches the delayed DLL reset signal DLLRST_REP in synchronism with the falling edge of the system clock. The multiplexer 146 selectively outputs the output of the external clock synchronizer 142 and the output of the latch 144 as an external reset signal EXTRST in response to a DLL disable signal DISDLL. When the external reset signal EXTRST is at a logic low level, the second clock counter 148 counts the rising edges of the system clock in response to the external reset signal EXTRST. An initial value of the second clock counter 148 is set to “0” and counts up to “7” and outputs the counting result signal EXTCNT<0:2>.
The result signals DLLCNT<0:2> and EXTCNT<0:2> outputted from the first and second clock counters 124 and 148 are inputted to the comparator 162 of the data output timing computation unit 160. The comparator 162 holds the result signal EXTCNT<0:2> outputted from the second clock counter 148 when the external command is inputted, generates a delay source signal LATB during a period at which the result signal EXTCNT<0:2> is equal to the result signal DLLCNT<0:2> outputted from the first clock counter 124, and outputs a delay signal LATENCYB in synchronism with the falling edge of the system clock. The signal generator 164 generates pulses in synchronism with the rising and falling edges of the system clock in response to the delay signal LATENCYB. The output enable signal output buffer 166 outputs a rising data signal RCLK_D0 in synchronism with the DLL clock RCLKDLL during an activation period of the pulse in response to one of the pulses outputted from the signal generator 164. The rising data signal RCLK_D0 is a basis of a data strobe signal (DQS) outputted together with data (Q0-Q7).
FIG. 2 is a timing diagram illustrating the operation of the data output control circuit of FIG. 1 in a low frequency environment.
Referring to FIG. 2, the data output control circuit generates the rising data signal RCLK_D0 for outputting data corresponding to the read command when the output reset signal OERST changes from the reset state to the deactivated state according to the operation mode of the semiconductor memory device.
First, the output reset signal OERST exits the reset state in response to the active signal, so that it becomes a logic low level. Thereafter, the DLL reset signal DLLRST becomes a logic low level in synchronism with the falling edge of the DLL clock RCLKDLL. The first clock counter 124 counts the rising edges of the DLL clock RCLKDLL in response to the DLL reset signal DLLRST and outputs the result signal DLLCNT<0:2>. The initial value of the first clock counter 124 using a 3-bit counter is 8−(CL−3). For example, when the CAS latency (CL) is 6, the initial value of the first clock counter 124 is 5.
The DLL reset signal DLLRST is delayed by the replica delay line 130 and then inputted to the second timing computation unit 140. The external clock synchronizer 142 receives the delayed DLL reset signal DLLRST_REP from the replica delay line 130 and transfers it in synchronization with the falling edge of the system clock EXTCLK. The multiplexer 146 outputs the delayed DLL reset signal DLLRST_REP as the external reset signal EXTRST. When the DLL circuit 450 of the semiconductor memory device is enabled, the multiplexer 146 outputs the output signal of the latch 144 as the external reset signal EXTRST. When the external reset signal EXTRST becomes a logic low level, the second clock counter 148 counts the rising edges of the system clock EXTCLK and outputs the counting result signal EXTCNT<0:2>. The initial value of the second clock counter 148 is 0 and counts up to 7 in a circular manner.
When the external read command RD is inputted, the semiconductor memory device generates a read pulse CASP10RD corresponding to the read command RD. When the read pulse CASP10RD is activated, the comparator 162 holds the result signal EXTCNT<0:2>=2 outputted from the second clock counter 148. Thereafter, when the result signal DLLCNT<0:2> outputted from the first clock counter 124 is 2, the comparator 162 outputs the delay signal LATENCYB. When the delay signal LATENCYB is at a logic low level, the signal generator 164 generates the output source signals from after the falling edge of the system clock EXTCLK. The output source signals ROUTEN, ROUTEN1, ROUTEN15, ROUNT2 and ROUNT25 are outputted in synchronism with the falling and rising edges of the system clock EXTCLK. The output enable signal output buffer 166 generates the rising data signal RCLK_D0 based on the DLL clock RCLKDLL while one signal ROUTEN15 of the output source signals is activated.
The output timing of the data corresponding to the read command RD is “AL+CL” when the DLL circuit 450 is in an enabled state and is “AL+(CL−1)+tAC” when the output timing of the data is in a disabled state. “AL” represents an additive latency”, and “tAC” represents an access time.
As described above, the initial value of the first clock counter 124 is 8−(CL−3). “8” means that the 3-bit counter is used to count eight from zero to seven. “CL−3” means a timing at which the delay signal LATENCYB is outputted from the comparator 162. If assuming that AL and tAC are 0 tCK as illustrated in FIG. 2, the rising data signal RCLK_D0 can be outputted at a (CL−1) timing by using the signal ROUTEN15 generated by delaying the delay signal LATENCYB by 1.5 tCK among the output source signals of the signal generator 164. Since it was assumed that CL=6, the rising data signal RCLK_D0 can be outputted after 5 tTCK from the input of the read command.
FIG. 3 is a timing diagram for explaining the problems of the data output control circuit of FIG. 1 in a high frequency environment. As illustrated, when the system clock has a high frequency, the data output timing of the data output control circuit in the same conditions of FIG. 2 is “AL+(CL−2)+tAC”, not “AL+(CL−1)+tAC.
The DLL reset signal DLLRST transferred from the first timing computation unit 120 to the second timing computation unit 140 is delayed by the replica delay line 130. The replica delay line 130 delays the DLL reset signal DLLRST by a delay modeling value of the system clock EXTCLK, without regard to the enabling or disabling of the DLL circuit 450 and the frequency of the system clock EXTCLK.
However, when the frequency of the system clock EXTCLK is high, the delay amount of the replica delay line 130 affects the output of the second clock counter 148 of the second timing computation unit 140. That is, due to the delay amount of the replica delay line 130, the delayed DLL reset signal DLLRST_REP may not be synchronized with a next falling edge of the system clock EXTCLK in the external clock synchronizer 142 of the second timing computation unit 140. In this case, the result outputted from the second clock counter 148 decrease by 1 than expected, and the data is outputted earlier than the expected timing by one period of the system clock EXTCLK. Consequently, as the frequency of the system clock increases, the frequency of the DLL CLK also increases. However, there is no change in the delay value of the replica delay line compensating the delay amount of the system clock within the semiconductor memory device. Thus, the conventional semiconductor memory device is not suitable for high frequency operation because it determines the data output timing by counting the system clock and the rising edges of the DLL clock.